NG RAD: Next-Generation RISC-V ASIC Design

Discipline: ECE

Advisor: Chung Yong Chan

The Side Channel Leakage Reduction Extension for a RISC-V core is an ASIC design feature intended to mitigate timing and power-based side-channel attacks. These attacks exploit physical leakage from hardware implementations of cryptographic algorithms to uncover secret information. This project introduces architectural defenses to improve the security of embedded processors used in sensitive applications. The design incorporated tactics such as boolean masking, noise-injection, and clock randomization to reduce the correlation between processed data and observable power or timing signals. This project carries through the full ASIC design flow process from RTL design and synthesis, to floorplanning, place and route, and physical verification. Both functional correctness and practical implementation are demonstrated. By improving hardware-level security while maintaining compatibility with open RISC-V architectures, this work contributes to more resilient and trustworthy computing platforms.

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